Field
The present disclosure relates generally to high-speed data communications, and more particularly, to encoding and decoding data over a multi-line parallel bus.
Background
High-speed interfaces are frequently used between circuits and components of mobile wireless devices and other complex apparatus. For example, certain devices may include processing, communications, storage and/or display devices that interact with one another through communications links. Some of these devices, including synchronous dynamic random access memory (SDRAM), may be capable of providing or consuming data and control information at processor clock rates. Other devices, such as display controllers, may require variable amounts of data at relatively low video refresh rates.
In system-on-chips (SoCs), various components are integrated on a single die. For example, a typical SoC in present mobile phones contains hundreds of components such as central and graphical processing units, memories, power management circuits, cellular and other wireless radios, etc. This integration of a large number of components onto a single silicon substrate results in smaller and lower-power processing units compared to traditional systems. All these components communicate with each other via metal wires known as interconnects or buses.
In non-SoC systems, components may also use interconnects or buses to communicate with each other. For example, a processor (e.g., central processing unit (CPU)) may communicate with a memory (e.g., DDR4 RAM) via an interconnect located on a printed circuit board (PCB).
Problems associated with these interconnects are transmission energy and delay. For a given technology, the width of the wire and the distance to the substrate remains fixed, and hence the capacitive coupling depends strongly on the distance between the wires. As the inter-wire spacing decreases, the coupling capacitance between adjacent wires increases, leading to increased crosstalk. This crosstalk between adjacent wires degrades the signal integrity and increases transmission energy and delay. Hence, the interconnects pose a major challenge to keep up with the demand for increasing data transfer rates. What is needed is a novel crosstalk avoidance scheme that improves signal integrity while decreasing transmission energy and delay.